System and method for low latency multi-market order book consolidation
US12406299B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 1, 2021 |
| Grant date | Sep 2, 2025 |
| Priority date | — |
| Expiry date | Jul 16, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06Q30/0201
- WIPO fieldIT methods for management
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides techniques and associated systems for low-latency integrated circuit-based feed handler circuits and multi-market order book consolidator circuits. In some embodiments, integrated circuit-based feed handler circuits described herein can be configured to store aggregate quantities of instruments and/or determine round-lot price levels in a parallel hardware configuration. In some embodiments, integrated circuit-based order book consolidator circuits described herein can be configured to determine consolidated prices across multiple market data feeds and/or for different groups of markets in parallel hardware configurations. According to various embodiments, aspects of the present disclosure can be implemented using one or more FPGAs, ASICs, and/or combinations thereof.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.