Timing sequence control circuit, timing sequence control method, and semiconductor memory
US12406706B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 14, 2023 |
| Grant date | Sep 2, 2025 |
| Priority date | — |
| Expiry date | Nov 15, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1093
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A timing sequence control circuit includes: a signal transmission module and a timing sequence compensation module, and the timing sequence compensation module is connected with the signal transmission module. Herein, the signal transmission module is configured to receive an initial sampling signal and transmit the initial sampling signal to generate a sampling signal. The timing sequence compensation module at least includes a compensation capacitor and is configured to receive an adjustable supply voltage, and perform compensation delay adjustment on the initial sampling signal according to the supply voltage and the compensation capacitor, so that the time difference between the sampling signal and a to-be-sampled Data (DQ) signal meets a preset requirement.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.