Self-selecting memory device, memory system having the same, and operating method thereof
US12406725B2 · kind B2 · utility
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6References
17Claims
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Key dates
| Filing date | Jun 14, 2023 |
| Grant date | Sep 2, 2025 |
| Priority date | — |
| Expiry date | Dec 28, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2013/0092
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An operating method of a self-selecting memory device, includes an operation of applying a first write pulse corresponding to a first state to a first memory cell during a first pulse width, and an operation of applying a second write pulse corresponding to a second state to a second memory cell during a second pulse width, wherein the first write pulse and the second write pulse have substantially opposite polarities, wherein the first pulse width is longer than the second pulse width.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.