Configuration control circuit of flash-typed field programmable gate array (FPGA) capable of suppressing programming interference
US12406733B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 7, 2023 |
| Grant date | Sep 2, 2025 |
| Priority date | — |
| Expiry date | Feb 26, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/01721
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A configuration control circuit of a flash-type FPGA capable of suppressing programming interference is provided. The configuration control circuit adds a programming selection circuit compared with a conventional configuration control circuit. When a programming operation is performed on a flash memory cell located in a target row and a target column, the programming selection circuit controls a path between a programming bit line (BL) voltage and a BL voltage obtaining terminal of the flash memory cell located in the target row and the target column to be turned on, and a path between the programming BL voltage and a BL voltage obtaining terminal of a flash memory cell located in another row and the target column to be turned off.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.