Semiconductor device
US12406942B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 28, 2023 |
| Grant date | Sep 2, 2025 |
| Priority date | — |
| Expiry date | Mar 28, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/143
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A device includes an integrated circuit, a first seal ring, a second seal ring, and a dielectric layer. The first seal ring surrounds the integrated circuit and includes a plurality of first seal portions separated from each other by a plurality of first gaps. The second seal ring surrounds the integrated circuit, between the integrated circuit and the first seal ring and includes a plurality of second seal portions separated from each other by a plurality of second gaps. The dielectric layer surrounds the first and second seal rings and includes a plurality of first filling portions in the first gaps, respectively, and a plurality of second filling portions in the second gaps, respectively. A connection line of one of the first filling portions and one of the second filling portions closest to said one of the first filling portions is not parallel to edges of the integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.