Quadrature divider error correction
US12407488B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 27, 2023 |
| Grant date | Sep 2, 2025 |
| Priority date | — |
| Expiry date | Sep 6, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0992
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit including a frequency divider configured to receive a plurality of first frequency input clock signals and provide a plurality of second frequency output clock signals, wherein the plurality of second frequency output clock signals are lower in frequency than the plurality of first frequency input clock signals, a phase detector configured to determine a difference between the plurality of second frequency output clock signals, a low pass filter configured to measure a clock signal spacing error associated with the plurality of second frequency output clock signals based on the difference between the plurality of second frequency output clock signals and to generate one or more control signals in response to the clock signal spacing error, and a control unit configured to generate one or more corrected first frequency input clock signals based on the one or more control signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.