Semiconductor devices having uppermost interconnection lines protruding beyond top surface of lower insulating layer on cell region
US12408350B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 12, 2022 |
| Grant date | Sep 2, 2025 |
| Priority date | — |
| Expiry date | Oct 26, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/85
Abstract
A semiconductor device includes a substrate including a cell region and a peripheral region, interconnection lines on the cell region and the peripheral region, the interconnection lines being spaced apart from the substrate in a first direction perpendicular to a top surface of the substrate, a lower insulating layer on the cell region and the peripheral region, the lower insulating layer covering the interconnection lines, and a top surface of the lower insulating layer on the cell region being at a lower height than top surfaces of uppermost interconnection lines of the interconnection lines, and data storage patterns on the lower insulating layer on the cell region, the data storage patterns being horizontally spaced apart from each other, and the data storage patterns being connected directly to the top surfaces of the uppermost interconnection lines on the cell region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.