Method and device for testing memory with instruction signal
US12411611B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2022 |
| Grant date | Sep 9, 2025 |
| Priority date | — |
| Expiry date | Dec 8, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and a device for memory testing, and a computer-readable storage medium are provided. In the method, an instruction signal is sent to the memory, the instruction signal comprising a randomly generated write instruction or read instruction; a valid Column Address Strobe (CAS) instruction for ensuring running of the instruction signal is randomly inserted before the instruction signal by detecting a specific type of the instruction signal, and at least one of a redundant CAS instruction or invalid command irrelevant to the instruction signal is randomly generated and inserted; and the memory is enabled to run the instruction signal, the inserted valid CAS instruction, and the at least one of the redundant CAS instruction or the invalid command, and the running of the memory is tested.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.