Precharge circuitry for use with bitlines
US12412623B2 · kind B2 · utility
0Cited by
5References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 8, 2022 |
| Grant date | Sep 9, 2025 |
| Priority date | — |
| Expiry date | Nov 10, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/413
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various implementations described herein are directed to a device having memory circuitry with bitlines coupled to an array of bitcells. The device may include precharge circuitry that precharges the bitlines during modes of operation including a standby mode of operation and an active mode of operation. In some instances, the precharge circuitry may include a low power mode of operation that prevents precharge of the bitlines during the standby mode of operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.