Patent · US Active

Ultra-low-voltage static random access memory (SRAM) cell for eliminating half-select disturbance under bit interleaving structure

US12412624B2 · kind B2 · utility

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8Claims

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Assignee

SHANGHAITECH UNIVERSITY · CN

Inventors

Yajun HA · Shanghai, CN
Yifei Li · East Walpole, US
Jian-Cheng Chen · Danei, TW
Hongyu Chen · Beijing, CN

Key dates

Filing date	Aug 14, 2023
Grant date	Sep 9, 2025
Priority date	—
Expiry date	Jan 31, 2044

Classification

Technology area (CPC G)Physics
CPC primaryG11C11/412
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An ultra-low-voltage static random access memory (SRAM) cell for eliminating half-select-disturbance under a bit interleaving structure includes a cross-coupled inverter pair, two N-type write transistors NM1 and NM2, two P-type write transistors PM1 and PM2, and two N-type transistors NM3 and NM4, where the two N-type transistors NM3 and NM4 form a readout path. The present disclosure can be applied to applications with a storage requirement at an ultra-low voltage, especially applications with certain requirements for an access speed and reliability of an SRAM at a low voltage. Compared with other different SRAM cells, the ultra-low-voltage SRAM cell can achieve higher read and write working frequencies with similar energy consumptions.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.