Flash memory for reducing reliability degradation of OS data due to SMT process
US12412633B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 13, 2023 |
| Grant date | Sep 9, 2025 |
| Priority date | — |
| Expiry date | Nov 28, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides apparatuses and methods for operating a flash memory for programming operating system (OS) data before an surface mount technology (SMT) process. In some embodiments, the method includes erasing a plurality of memory cells in a memory block, reducing a lateral charge loss of the plurality of memory cells due to high temperature degradation during the SMT process by applying a pre-program voltage to word lines coupled to the memory block, and performing multi-bit programming of the OS data in the plurality of memory cells, prior to performing the SMT process. The applying of the pre-program voltage causes threshold voltages of the plurality of memory cells to increase.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.