Large area synthesis of cubic phase gallium nitride on silicon
US12412751B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 18, 2023 |
| Grant date | Sep 9, 2025 |
| Priority date | — |
| Expiry date | Jul 1, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10H20/825
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A wafer includes a buried substrate; a first layer of silicon (100) disposed on the buried substrate that includes silicon sidewalls (111) at an angle to the buried substrate and that form a bottom of each of multiple U-shaped grooves; a second layer of patterned oxide disposed on the silicon (100) that provides vertical sidewalls of each U-shaped groove formed within the first and second layers; a third layer of a buffer covering the first layer and partially covering the second layer partway up the vertical sidewalls; and multiple gallium nitride (GaN)-based structures disposed within the multiple U-shaped grooves, the multiple GaN-based structures each including cubic gallium nitride (c-GaN) formed at merged growth fronts of hexagonal gallium nitride (h-GaN) that extend from the silicon sidewalls (111).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.