Phase locked loop circuit and semiconductor device including the same
US12413234B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 13, 2023 |
| Grant date | Sep 9, 2025 |
| Priority date | — |
| Expiry date | Dec 4, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0995
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase locked loop circuit and a semiconductor device are provided. The phased locked loop circuit includes a reference current generator configured to generate a summed compensation current in which at least one of a process change, a temperature change or a power supply voltage change are compensated and output the summed compensation current as a reference current, a current digital-to-analog converter configured to convert the reference current into a control current in accordance with a digital code and a voltage control oscillator configured to generate a signal based on the control current, wherein the summed compensation current is based on weighted-averaging a first type compensation current and a second type compensation current in response to at least one of the process change, the temperature change or the power supply voltage change.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.