Segmented capacitance calibration circuit applied in pure capacitor array structure
US12413239B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 26, 2023 |
| Grant date | Sep 9, 2025 |
| Priority date | — |
| Expiry date | May 29, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/466
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A segmented capacitance calibration circuit applied in a pure capacitor array structure includes a first calibration unit, a second calibration unit and a selection switch which are all connected with a scaling capacitor. The first and second calibration units include at least one capacitor, and the selection switch is configured to select the first or second calibration unit to be connected to the pure capacitor array structure. When the first calibration unit is connected to the pure capacitor array structure and in parallel with the scaling capacitor, a negative error calibration is performed on the scaling capacitor. When the second calibration unit is connected to the pure capacitor array structure and in series with the scaling capacitor, a positive error calibration is performed on the scaling capacitor. The nonlinear problem caused by the precision error of the scaling capacitor in the pure capacitor array structure is solved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.