Synchronizing systems on a chip using time synchronization messages
US12413325B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 4, 2021 |
| Grant date | Sep 9, 2025 |
| Priority date | — |
| Expiry date | Mar 8, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0038
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
An electronic eyewear device includes first and second systems on a chip (SoCs) having independent time bases and an inter-SoC interface that connects the first and second SoCs. The operations of the first and second SoCs are synchronized by aligning the time bases for the SoCs using a modified PTP technique. The technique includes the second SoC receiving a time synchronization message from the first SoC over the inter-SoC interface, recording a local timestamp of receipt of the time synchronization message, receiving a master timestamp corresponding to a timestamp recorded by the first SoC corresponding to the time of sending the time synchronization message by the first SoC, and calculating a time offset between the local timestamp and the master timestamp. The time bases of the first SoC and second SoC are then aligned using the calculated time offset. To account for transmission delays, multiple time offsets may be averaged.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.