Semiconductor structure and manufacturing method thereof
US12414285B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 15, 2022 |
| Grant date | Sep 9, 2025 |
| Priority date | — |
| Expiry date | Jan 26, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/31
Abstract
The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a base including bit lines arranged at intervals and extending along a first direction, and a semiconductor channel located on partial top surfaces of the bit lines, where along a direction from the bit line to the semiconductor channel, the semiconductor channel includes a first region, a second region, and a third region that are arranged sequentially; a dielectric layer located between adjacent two of the bit lines and on a sidewall of the semiconductor channel; a gate structure at least surrounding the dielectric layer in the second region and extending along a second direction, where the first direction is different from the second direction; an electrical connection layer covering a top surface of the third region and extending to a partial sidewall of the semiconductor channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.