Integrated circuit including at least one capacitive element and corresponding manufacturing method
US12414360B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 19, 2022 |
| Grant date | Sep 9, 2025 |
| Priority date | — |
| Expiry date | Nov 11, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A capacitive element includes a first conductive layer delimited by an outline and a low voltage dielectric layer covering the first conductive layer. A second conductive layer covers the low voltage dielectric layer and includes: a first portion located over a central zone of the first conductive layer which forms a first capacitor electrode; and a second portion located over the first conductive layer at the inner border of the entire outline of the first conductive layer, and over the front face at the outer border of the entire outline of the first conductive layer. The first portion and the second portion of the second conductive layer are electrically separated by an annular opening extending through the second conductive layer. The first conductive layer is electrically connected to the second portion of the second conductive layer to form a second capacitor electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.