Circuitry and methods for informing indirect prefetches using capabilities
US12417099B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 2, 2022 |
| Grant date | Sep 16, 2025 |
| Priority date | — |
| Expiry date | Dec 9, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, methods, and apparatuses for implementing capability-based indirect prefetching are described. In certain examples, a hardware processor comprises an execution circuit to execute an instruction that generates a memory access request for an element in memory via a first capability; a capability management circuit to check the first capability for the memory access request, the first capability comprising an address field of the element in the memory, a validity field, and a bounds field that is to indicate a lower bound and an upper bound of a first object to which the first capability authorizes access; a cache; and a prefetch circuit to: prefetch an additional element of the first object from the memory based on the first capability, determine if the additional element is a second capability comprising an address field of a second element in the memory, a validity field, and a bounds field that is to indicate a lower bound and an upper bound of a second object to which the second capability authorizes access, and prefetch the second element from the memory to the cache based on the additional element being the second capability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.