Instructions for structured-sparse tile matrix FMA
US12417100B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 1, 2022 |
| Grant date | Sep 16, 2025 |
| Priority date | — |
| Expiry date | Oct 1, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F17/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, methods, and apparatuses relating sparsity based FMA. In some examples, an instance of a single FMA instruction has one or more fields for an opcode, one or more fields to identify a source/destination matrix operand, one or more fields to identify a first plurality of source matrix operands, one or more fields to identify a second plurality of matrix operands, wherein the opcode is to indicate that execution circuitry is to select a proper subset of FP8 data elements from the first plurality of source matrix operands based on sparsity controls from a first matrix operand of the second plurality of matrix operands and perform a FMA.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.