Memory system, method of operating the same, and electronic system including the same
US12417143B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2023 |
| Grant date | Sep 16, 2025 |
| Priority date | — |
| Expiry date | Dec 26, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1048
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system includes a plurality of volatile memory devices and a memory controller. The memory controller causes different amounts of error correction parity information to be generated depending on a request from a host device and depending on failed memory cell counts. The memory controller includes an error correction level (ECL) manager configured to receive cache line data from the host device through the host interface, and output an error correction code (ECC) control signal indicating one of a first correction level and a second correction level. The correction levels are based on cell reliability information and data reliability request information. The data reliability request information is associated with the cache line data. An ECC engine generates first parity symbols associated with the cache line data, and may, depending on the ECC control signal, generate additional parity symbols.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.