Voltage mode weak-PUF circuit with rich challenge-response pairs
US12417321B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 22, 2024 |
| Grant date | Sep 16, 2025 |
| Priority date | — |
| Expiry date | Jun 13, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2221/2103
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A voltage mode weak-PUF circuit with rich challenge-response pairs comprises four decoders, two PUF arrays, a sequential control circuit and a voltage comparator. One-to-two PUF arrays are used to replace existing one-to-one PUF arrays to increase the number of challenge-response pairs by 2N times, from 2N realized by the one-to-one PUF arrays to 2N×2N, wherein N=a+b. Each PUF cell comprises m*n PUF cells and n transmission gates, and adopts a simple common-source amplifier structure formed by a first PMOS transistor, a first NMOS transistor and a second NMOS transistor, wherein any one PUF cell in one PUF array can be compared with any one PUF cell in the other PUF array to generate an output response. The number of output responses is 2N, so the proportion of the PUF cells for generating one challenge-response pair is 2N/2N=1/2N, and the reuse rate of the same PUF cell is merely 1/2N.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.