Stacked 3D memory architecture for power optimization
US12417817B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 11, 2023 |
| Grant date | Sep 16, 2025 |
| Priority date | — |
| Expiry date | Dec 5, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/785
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A headset includes a camera a 3D stacked memory configured to store image data captured by the camera, and a System-on-Chip (SoC) configured to process the image data stored in the 3D stacked memory. The 3D stacked memory includes a plurality of first drivers/receivers and a plurality of memory banks that are accessible in parallel. Each memory bank is accessible via a corresponding first driver/receiver. The SoC includes a memory controller with a plurality of second drivers/receivers. The plurality of the second drivers/receivers of the SoC are respectively connected to the plurality of the first drivers/receivers of the 3D stacked memory by a plurality of channels. The SoC and the 3D stacked memory are vertically stacked together. The plurality of the memory banks include at least eight memory banks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.