Sealing ring, stacked structure, and method for manufacturing sealing ring
US12417952B2 · kind B2 · utility
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1References
16Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 27, 2022 |
| Grant date | Sep 16, 2025 |
| Priority date | — |
| Expiry date | Sep 30, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of the disclosure provide a sealing ring, a stacked structure, and a method for manufacturing a sealing ring. The sealing ring is arranged at a periphery of a device area of a chip, and includes an inner ring structure, a middle ring structure, and an outer ring structure. The middle ring structure is connected to the device area through a doped well. The doped well is located in part of a substrate corresponding to the inner ring structure and the middle ring structure, and is isolated from the inner ring structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.