Integrated circuit unit and wafer with integrated circuit units
US12417986B2 · kind B2 · utility
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31Claims
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Key dates
| Filing date | Mar 29, 2022 |
| Grant date | Sep 16, 2025 |
| Priority date | — |
| Expiry date | Dec 6, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/528
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Integrated circuit (“IC”) unit and a wafer for fabricating IC units. The wafer has a first surface and a second surface opposite to the first surface. A redistribution metal layer may be formed on the first surface and may be patterned to have a redistribution metal layer pattern. A backside metal layer may be formed on the second surface and patterned to have a backside metal layer pattern so that the backside metal layer may be adapted to generate a backside stress on the wafer to at least partially offset a front side stress generated by the redistribution metal layer on the wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.