Method and system for cooperatively suppressing common-mode voltage and current harmonics of coupled three-level inverter
US12418245B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 25, 2025 |
| Grant date | Sep 16, 2025 |
| Priority date | — |
| Expiry date | Apr 25, 2045 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M1/123
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
The present invention provides a method for cooperatively suppressing a common-mode voltage and current harmonics of coupled three-level inverters, comprising: based on amplitude and phase angle of reference voltage vector, determining sector and region in which the reference voltage vector is located; selecting four basic voltage vectors with low common-mode voltage amplitudes to synthesize the reference voltage vector; writing volt-second balance equation based on selected basic voltage vectors, and calculating duty cycles thereof; and based on sector and region in which reference voltage vector is located, set value of voltage difference across capacitors on direct current side, and actual value of voltage difference across capacitors on direct current side, (1) updating duty cycles of basic voltage vectors, to realize separate control of capacitor voltage; and (2) designing and converting switching sequence into PWM drive signal of power switch, to control the coupled three-level inverter to operate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.