Programmable self-biasing inverter for correcting duty cycle distortion
US12418283B2 · kind B2 · utility
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19Claims
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Key dates
| Filing date | Dec 20, 2023 |
| Grant date | Sep 16, 2025 |
| Priority date | — |
| Expiry date | Feb 21, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1565
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock conditioning circuit includes a duty cycle correction circuit. The duty cycle correction circuit has a first input capacitor, a first self-biasing inverter and a variable capacitor. The first self-biasing inverter has an input coupled to the first input capacitor. The variable capacitor may be coupled to the first input capacitor. The variable capacitor may be configured to receive a first clock signal. A capacitance of the variable capacitor may be programmable by a capacitance control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.