Connection assembly, board-level architecture, and computing device
US12418985B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 27, 2023 |
| Grant date | Sep 16, 2025 |
| Priority date | — |
| Expiry date | Apr 7, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10984
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The technology of this disclosure relates to a connection assembly, a board-level architecture, and a computing device. The connection assembly is configured to connect a semiconductor wafer and a lower layer substrate that are disposed opposite to each other, and includes an insulator structure and a plurality of connection terminals that are disposed at spacings. A first end and a second end of any one of the plurality of connection terminals each are provided with a welding structure. The first end is welded to the semiconductor wafer, and the second end is welded to the lower layer substrate. The insulator structure includes a plurality of empty slots provided at spacings. Positions of the plurality of empty slots are in a one-to-one correspondence with positions of the plurality of connection terminals. Any one of the plurality of connection terminals is disposed in any empty slot, to fasten a position of the connection terminal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.