Vertical gate all around transistor having dual gate structures
US12419034B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 22, 2022 |
| Grant date | Sep 16, 2025 |
| Priority date | — |
| Expiry date | Feb 1, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/837
Abstract
A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure includes: a substrate, a dielectric layer, a first gate structure and a second gate structure. The substrate includes discrete semiconductors arranged at a top of the substrate and extending in a vertical direction. The first gate structure is arranged in a first region of the semiconductor pillar and surrounds the semiconductor pillar. The second gate structure is arranged in a second region of the semiconductor pillar and includes a ring structure and at least one bridge structure. The ring structure surrounds the semiconductor pillar, and the at least one bridge structure penetrates through the semiconductor pillar and extends to an inner wall of the ring structure in a penetrating direction. The dielectric layer is located between the first gate structure and the semiconductor pillar, and between the second gate structure and the semiconductor pillar.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.