Barrier structure configured to increase performance of III-V devices
US12419074B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 5, 2022 |
| Grant date | Sep 16, 2025 |
| Priority date | — |
| Expiry date | Jan 19, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/343
Abstract
Various embodiments of the present disclosure are directed toward an integrated chip including an undoped layer overlying a substrate. A first barrier layer overlies the undoped layer. A doped layer overlies the first barrier layer. Further, a second barrier layer overlies the first barrier layer, where the second barrier layer is laterally offset from a perimeter of the doped layer by a non-zero distance. The first and second barrier layers comprise a same III-V semiconductor material. A first atomic percentage of a first element within the first barrier layer is less than a second atomic percentage of the first element within the second barrier layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.