Electrostatic discharge protection circuit
US12419115B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 14, 2022 |
| Grant date | Sep 16, 2025 |
| Priority date | — |
| Expiry date | Dec 14, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/911
Abstract
An ESD protection circuit includes a buffer circuit, a driving circuit, and a power-clamping circuit. The buffer circuit includes first and second transistors having a first conductivity type coupled in a cascade configuration between a first node and a first power supply node. A bonding pad is coupled to the first node. The drive circuit determines a state of at least one of the first and second transistors according to a control voltage. The drive circuit includes a third transistor having a second conductivity type, which is coupled between a second power supply node and a gate of the first transistor and is controlled by the control signal. The power-clamping circuit is coupled to the bonding pad and a gate of the third transistor at a second node. The control voltage is generated at the second node and determined by a voltage at the bonding pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.