Processing apparatus and method of processing add operation therein
US12423055B2 · kind B2 · utility
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3References
11Claims
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Key dates
| Filing date | Nov 14, 2019 |
| Grant date | Sep 23, 2025 |
| Priority date | — |
| Expiry date | Mar 11, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/4824
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of processing an add operation in a processing apparatus includes acquiring sub-operands from input operands each having an n-bit precision, acquiring intermediate addition results by performing add operations of sub-operands in parallel by using adders, bit-shifting each of the intermediate addition results such that the intermediate addition results correspond to original bit positions in the input operands, and outputting a final addition result of the add operations of the input operands based on the bit-shifted intermediate addition results.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.