Systolic array with input reduction to multiple reduced inputs
US12423058B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2021 |
| Grant date | Sep 23, 2025 |
| Priority date | — |
| Expiry date | Apr 23, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8046
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods are provided to perform multiply-accumulate operations of reduced precision numbers in a systolic array. Each row of the systolic array can receive reduced inputs from a respective reducer. The reducer can receive a particular input and generate multiple reduced inputs from the input. The reduced inputs can include reduced input data elements and/or a reduced weights. The systolic array may lack support for inputs with a first bit-length and the reducers may reduce the bit-length of a given input from the first bit-length to a second shorter bit-length and provide multiple reduced inputs with second shorter bit-length to the array. The systolic array may perform multiply-accumulate operations on each unique combination of the multiple reduced input data elements and the reduced weights to generate multiple partial outputs. The systolic array may sum the partial outputs to generate the output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.