Data processing network with super home node
US12423237B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 14, 2023 |
| Grant date | Sep 23, 2025 |
| Priority date | — |
| Expiry date | May 21, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1048
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A super home node of a first chip of a multi-chip data processing system manages coherence for both local and remote cache lines accessed by local caching agents and local cache lines accessed by caching agents of one or more second chips. Both local and remote cache lines are stored in a shared cache, and requests are stored in shared point-of-coherency queue. An entry in a snoop filter table of the super home node includes a presence vector that indicates the presence of a remote cache line at specific caching agents of the first chip or the presence of a local cache line at specific caching agents of the first chip and any caching agent of the second chip. All caching agents of the second chip are represented as a single caching agent in the presence vector.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.