Nonvolatile memory device and memory system
US12423246B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 11, 2024 |
| Grant date | Sep 23, 2025 |
| Priority date | — |
| Expiry date | Mar 14, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0679
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nonvolatile memory device includes a memory cell array to store an original setting data, a page buffer circuit connected to the memory cell array through a plurality of bit-lines, a secure buffer and a control circuit. The secure buffer includes an access control circuit and a plurality registers with restricted access, and the plurality registers store the original setting data that is dumped-down from the memory cell array through the page buffer circuit in an initialization sequence. The control circuit controls the page buffer circuit and the secure buffer. The plurality registers include a first register and second registers. The access control circuit, in response to the first register being accessed, accesses at least a portion of the second registers concurrently with accessing the first register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.