Interrupt latency resilient UART driver
US12423254B2 · kind B2 · utility
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1References
16Claims
0Family size
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Key dates
| Filing date | Aug 17, 2023 |
| Grant date | Sep 23, 2025 |
| Priority date | — |
| Expiry date | Aug 22, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1673
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method of reducing data loss in a system utilizing a bus protocol that does not support flow control is disclosed. The peripheral device utilizes a spill buffer which is used to capture any data sent by the host before the peripheral device is able to properly configure the DMA controller. Additionally, the peripheral device includes a recovery routine, which is a software program that parses the spill buffer and extracts any headers or payloads that are contained therein. Using the spill buffer and recovery routine, the baud rate of the bus interface may be increases without incurring any increase in data loss.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.