Reception circuit and smart card including the same
US12423533B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 19, 2023 |
| Grant date | Sep 23, 2025 |
| Priority date | — |
| Expiry date | Sep 19, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06K19/0723
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides systems and devices including reception circuits for communications between smart cards and card readers. In some embodiments, a reception circuit of a smart card includes a first circuit and a second circuit. The first circuit is configured to receive a wireless signal including a pause, and restore the wireless signal to a clock signal. The second circuit is configured to charge a voltage of a first node based on a first logic level of the clock signal, compare the voltage of the first node with a predefined reference voltage, and output, based on the comparison of the voltage of the first node, a synchronization signal indicating a rising starting time point of the pause of the wireless signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.