Neural network chip for ear-worn device
US12423558B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 16, 2024 |
| Grant date | Sep 23, 2025 |
| Priority date | — |
| Expiry date | May 16, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04R25/505
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A hearing aid may include a neural network chip having tiles arranged in an array, each tile including memory, 16-128 multiplier-accumulator circuits (MACs), and routing circuitry. The memory of each tile may be configured to store a portion of elements of a matrix A comprising weights of a recurrent neural network. Each tile may be configured to receive and store elements of an activation vector X, and all tiles in a column of the array may be configured to receive the same elements of X. The plurality of tiles may be configured to perform a matrix-vector multiplication A*X by performing multiply-and-accumulate sub-operations in parallel among the plurality of tiles. The routing circuitry from the tiles in each respective row of tiles may be configured to combine results of the multiply-and-accumulate sub-operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.