Memory and operating method therefor
US12424268B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 19, 2023 |
| Grant date | Sep 23, 2025 |
| Priority date | — |
| Expiry date | Aug 18, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4096
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory includes: a memory cell array; a first column decoder, coupled to the memory cell array and configured to perform a write operation on the memory cell array; a second column decoder, coupled to the memory cell array and configured to perform a read operation on the memory cell array; and a read amplifier, the read amplifier and the second column decoder being located on two opposite sides of the memory cell array, the read amplifier being coupled to the memory cell array and configured to receive read data information output by the memory cell array based on the read operation. The read amplifier, the first column decoder, the memory cell array and the second column decoder are arranged in a first direction, and the first column decoder and the second column decoder are located on two opposite sides of the memory cell array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.