Static random-access memory (SRAM) device and related SRAM-based compute-in-memory devices
US12424275B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 26, 2023 |
| Grant date | Sep 23, 2025 |
| Priority date | — |
| Expiry date | Mar 27, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B10/125
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An SRAM cell includes a first inverter cross-coupled to a second inverter. The first inverter includes a first pull-up transistor and a first pull-down transistor, having coupled drains that define a first storage node. The SRAM cell further includes a first N-type pass-gate transistor having a first drain coupled to a write bit line, a first source coupled to the first storage node, and a first gate coupled to a first write word line. The SRAM cell further includes a first P-type pass-gate transistor having a second drain coupled to the write bit line and a second source coupled to the first storage node. The SRAM cell further includes a P-type transistor having a third drain, coupled to a second gate of the first P-type pass-gate transistor, a third source coupled to a second write word line, and a third gate coupled to an enable signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.