Via manufacturing method
US12424540B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 5, 2022 |
| Grant date | Sep 23, 2025 |
| Priority date | — |
| Expiry date | Apr 3, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76807
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is presented for manufacturing an insulated conductive via. The via crosses a first stack of layers to reach a first layer. A first cavity is formed partially extending into the first stack of layers. A second stack of layers is formed over the first stack of layers and in the first cavity. The second stack of layers includes an etch stop layer and an insulating layer. A second cavity is then formed extending completely through first and second stacks of layers to reach the first layer. An insulating liner then covers the walls and bottom of the second cavity. The insulating liner is then anisotropically etched, and the second cavity is filled by a conductive material forming the core of the via.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.