Clock distribution jitter reduction systems and methods
US12425005B2 · kind B2 · utility
0Cited by
6References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 8, 2024 |
| Grant date | Sep 23, 2025 |
| Priority date | — |
| Expiry date | Apr 3, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/20
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Embodiments of the invention relate to a clock generation and distribution circuit (“clock circuit”) according to various embodiments of the present disclosure. The clock circuit comprises active impedance reduction circuits which improves bandwidth and jitter performance of the clock circuit by lowering the small-signal impedance within the clock circuit. In certain embodiments, an activation element is positioned at a node along a transmission path to cause a reduction in impedance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.