Multi-chip synchronization in sensor applications
US12425178B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 21, 2023 |
| Grant date | Sep 23, 2025 |
| Priority date | — |
| Expiry date | Dec 6, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0807
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A system may include a plurality of devices coupled to one another via a shared digital wired communication link, the plurality of devices comprising a first device configured to periodically transmit a synchronization packet onto the shared digital wired communication link to synchronize other of the plurality of devices to a reference clock of the first device, a second device configured to receive the synchronization packet and transmit one or more first data packets onto the shared digital wired communication link in response to the synchronization packet, and a third device configured to receive the synchronization packet and transmit one or more second data packets onto the shared digital wired communication link in response to the synchronization packet and the one or more second data packets.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.