Semiconductor memory device and method of fabricating the same
US12426243B2 · kind B2 · utility
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24References
20Claims
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Key dates
| Filing date | May 3, 2022 |
| Grant date | Sep 23, 2025 |
| Priority date | — |
| Expiry date | Jun 27, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/485
Abstract
A semiconductor memory device includes a device isolation pattern on a substrate and defining a first active section, a first storage node pad on the first active section, a word line in the substrate and extending across the first active section, a bit line on the first storage node pad and crossing over the word line, a storage node contact on one side of the bit line and adjacent to the first storage node pad, and an ohmic layer between the storage node contact and the first storage node pad. A bottom surface of the ohmic layer is rounded.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.