Semiconductor structure including a plurality of semicondcutor pillars and bit line isolation trenches and method for forming same
US12426256B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jul 4, 2022 |
| Grant date | Sep 23, 2025 |
| Priority date | — |
| Expiry date | Nov 7, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/485
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a semiconductor structure includes: providing a semiconductor substrate including a plurality of first semiconductor pillars and bit line isolation trenches arranged at intervals in a first direction; in which the bit line isolation trenches extend in a second direction, the first direction being perpendicular to the second direction; forming a bit line isolation layer in a bit line isolation trench; in which a gap is provided between the bit line isolation layer and the bit line isolation trench, in which the gap is located at a bottom corner of the bit line isolation trench and extends in the second direction, and exposes part of the bottom of the bit line isolation trench; etching a first semiconductor pillar in the first direction through the gap to form a bit line trench; forming a bit line in the bit line trench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.