Method of forming capacitor hole, and semiconductor structure
US12426282B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 27, 2022 |
| Grant date | Sep 23, 2025 |
| Priority date | — |
| Expiry date | Jan 18, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/716
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a method of forming a capacitor hole, and a semiconductor structure. The method includes: providing a substrate, where an electrode is formed in the substrate; forming a pattern definition layer on a surface of the substrate; sequentially forming three sets of trenches in the pattern definition layer, where the three sets of trenches intersect with each other at 120°, and a hexagonal hole is formed at an intersection position in the pattern definition layer; etching the substrate along the hexagonal hole by the pattern definition layer as a mask, to form a capacitor hole in the substrate, where a bottom of the capacitor hole is round under a loading effect of etching, and the electrode is exposed at the bottom of the capacitor hole.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.