Semiconductor devices and methods of manufacturing semiconductor device
US12426302B2 · kind B2 · utility
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Key dates
| Filing date | Jan 18, 2023 |
| Grant date | Sep 23, 2025 |
| Priority date | — |
| Expiry date | Mar 16, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/106
Abstract
A semiconductor device comprises: a SiC epitaxial layer and a first recess. The SiC epitaxial layer has: a p-type well region; a heavily doped n-type region on a surface of the p-type well region; and a heavily doped p-type region below the heavily doped n-type region and within the p-type well region. The first recess is formed in the heavily doped p-type region and the heavily doped n-type region, wherein a depth of the first recess exceeds a depth of the heavily doped n-type region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.