Semiconductor device and method of manufacturing semiconductor device
US12426318B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2022 |
| Grant date | Sep 23, 2025 |
| Priority date | — |
| Expiry date | Mar 9, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/875
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a semiconductor device including an n-type gallium oxide semiconductor layer that has a center region and a peripheral region having a lower donor density than the center region, an electrode layer that is laminated on the n-type gallium oxide semiconductor layer, and forms Schottky junction with the n-type gallium oxide semiconductor layer in the center region as viewed from a lamination direction, and a first p-type nickel oxide semiconductor layer that is laminated on the n-type gallium oxide semiconductor layer such that the first p-type nickel oxide semiconductor layer is partially positioned between the n-type gallium oxide semiconductor layer and the electrode layer, and has an outer peripheral end portion on a peripheral region side in the peripheral region as viewed from the lamination direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.