Multi-gate transistor channel height adjustment
US12426347B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 4, 2022 |
| Grant date | Sep 23, 2025 |
| Priority date | — |
| Expiry date | Sep 20, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0193
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method includes providing a semiconductor substrate having a first region and a second region, epitaxially growing a semiconductor layer above the semiconductor substrate, patterning the semiconductor layer to form a first fin in the first region and a second fin in the second region, and depositing a dielectric material layer on sidewalls of the first and second fins. The method also includes performing an anneal process in driving dopants into the dielectric material layer, such that a dopant concentration in the dielectric material layer in the first region is higher than that in the second region, and performing an etching process to recess the dielectric material layer, thereby exposing the sidewalls of the first and second fins. A top surface of the recessed dielectric material layer in the first region is lower than that in the second region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.