Image sensor with stack structure in which two semiconductor chips are combined with each other
US12426396B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 9, 2022 |
| Grant date | Sep 23, 2025 |
| Priority date | — |
| Expiry date | Dec 5, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/807
Abstract
An image sensor includes: a first semiconductor chip having a pixel region, a peripheral region, and a first wiring layer; and a second semiconductor chip combined with the first semiconductor chip, and including a second wiring layer, wherein the pixel region includes an active pixel region and a dummy pixel region, wherein the pixels are separated from one another by deep trench isolations (DTI) passing through a silicon layer, wherein a backside contact applying a negative (−) voltage to a conductive layer of each of the DTIs is arranged in the dummy pixel region and passes through the silicon layer, wherein the backside contact contacts the conductive layer of each of the DTIs, and wherein a through via is formed in the peripheral region, and wiring lines of the first wiring layer are connected to wiring lines of a second wiring layer through the through via.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.