Patent · US Active

Interface built in test failure detection apparatus

US12429518B2 · kind B2 · utility

0Cited by
4References
20Claims
0Family size

Assignee

Inventors

Key dates

Filing dateJul 19, 2023
Grant dateSep 30, 2025
Priority date—
Expiry dateApr 7, 2044

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG01R31/2884
  • WIPO fieldMeasurement
  • WIPO sectorInstruments

Abstract

An interface BIT failure detection circuit includes a sequencing circuit and a multiplexer. The sequencing circuit configured to generate the sequence selection signal. The multiplexer is in signal communication with the sequencing circuit, and includes a plurality of interface input. Each interface input corresponds to an interface of a device under test. The sequence selection signal is configured to control the MUX to sequentially select each of the interface inputs. The MUX includes an output terminal configured to output a test signal configured to indicate whether or not at least one fault corresponding to one or more of the interface inputs or a main power supply exists.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.